DocumentCode
74360
Title
Prevention slot flow-control mechanism for low latency torus network-on-chip
Author
Joshi, Akanksha ; Venkatesh, P. ; Mutyam, Madhu
Author_Institution
Comput. Sci. & Eng., IIT Madras, Chennai, India
Volume
7
Issue
6
fYear
2013
fDate
Nov-13
Firstpage
304
Lastpage
316
Abstract
The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and maintain the simplicity of a mesh topology, torus topology is proposed. As torus topology has an inherent circular dependency, additional effort is needed to prevent deadlock, even if deadlock free routing algorithms are used. The authors propose a novel flow-control mechanism to address cost/performance constraints in torus networks and ensure deadlock freedom. They achieve flow-control by using a prevention mechanism and ensure deadlock freedom while requiring only a single packet buffer per input port. They simplify the router design by having a simple switch allocator that prioritises in-flight packets, and a single packet buffer per input port that eliminates the need for virtual channels. They also propose a mechanism to avoid starvation that can arise because of the prioritised arbitration. Experimental validation reveals that the authors design achieves significant improvement in throughput, as compared with the traditional design, while using significantly fewer buffers.
Keywords
mesh generation; network-on-chip; topology; deadlock free routing algorithms; inherent circular dependency; low latency torus network-on-chip; mesh topology; novel flow-control mechanism; prevention slot flow-control mechanism; simple switch allocator; single packet buffer; torus topology; virtual channels;
fLanguage
English
Journal_Title
Computers & Digital Techniques, IET
Publisher
iet
ISSN
1751-8601
Type
jour
DOI
10.1049/iet-cdt.2013.0012
Filename
6651341
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