Exploring Spin-Transfer-Torque Devices for Logic Applications

As CMOS nears the end of the projected scaling roadmap, significant effort has been devoted to the search for new materials and devices that can realize memory and logic. Spintronics, which uses the spin of electrons to represent and manipulate information, is one of the promising directions for the post-CMOS era. While the potential of spintronic memories is relatively well known, realizing logic remains an open and critical challenge. All spin logic (ASL) is a recently proposed logic style that realizes Boolean logic using spin-transfer-torque devices based on the principle of nonlocal spin torque. ASL has advantages such as density, nonvolatility, and low operating voltage. However, it also suffers from drawbacks such as low speed and static power dissipation. Recent work has shown that, in the context of simple arithmetic circuits (adders and multipliers), the efficiency of ASL can be greatly improved using techniques that utilize its unique characteristics. An evaluation of ASL across a broad range of circuits, considering the known optimization techniques, is an important next step in determining its viability. In this paper, we propose a systematic methodology for the synthesis of ASL circuits. Our methodology performs various optimizations that benefit ASL, such as intracycle power gating, stacking of ASL nanomagnets, and fine-grained logic pipelining. We utilize the proposed methodology to evaluate the suitability of ASL implementations for a wide range of benchmarks, viz., random combinational and sequential logic, digital signal processing circuits, and the Leon SPARC3 general-purpose processor. Based on our evaluation, we identify: 1) the large current requirement of nanomagnets at fast switching speeds; 2) the static power dissipation in the all-metallic devices; and 3) the short spin flip length in interconnects as key bottlenecks that limit the competitiveness of ASL. We further evaluate the impact of various potential improvements in device paramete- s on the efficiency of ASL.