Optimization-based transistor sizing

Author

Shyu, Jyuo-Min ; Sangiovanni-Vincentelli, Alberto ; Fishburn, John P. ; Dunlop, Alfred E.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

23

Issue

2

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

400

Lastpage

409

Abstract

A combined heuristic and mathematical programming approach to transistor sizing is presented. A fast heuristic algorithm is used to obtain an initial sizing of the circuit and convert the transistor sizing problem into a nonlinear optimization problem. The problem is then solved, in spaces of reduced dimensionality, by mathematical programming techniques. To cope with the nondifferentiability of the circuit delays, the concept of generalized gradients is proposed to compute the delay sensitivities. Experiments justify the use of this sensitivity computation technique and show that the approach is a good compromise between the speed of the heuristic algorithm and the power of mathematical programming.<>

Keywords

CMOS integrated circuits; circuit layout CAD; integrated circuit technology; optimisation; CMOS; VLSI circuit performance optimization; circuit delays; delay sensitivities; generalized gradients; heuristic algorithm; mathematical programming approach; nonlinear optimization problem; scaling; sensitivity computation technique; spaces of reduced dimensionality; transistor sizing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.1000

Filename

1000