• DocumentCode
    745067
  • Title

    Power characteristics of inductive interconnect

  • Author

    El-Moursy, Magdy A. ; Friedman, Eby G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
  • Volume
    12
  • Issue
    12
  • fYear
    2004
  • Firstpage
    1295
  • Lastpage
    1306
  • Abstract
    The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.
  • Keywords
    CMOS logic circuits; RLC circuits; circuit optimisation; integrated circuit interconnections; minimisation; power consumption; CMOS logic circuits; RLC circuits; dynamic power; inductive interconnect line; matching condition; power characteristics; power consumption; short circuit power dissipation; signal transition time; transient power dissipation; wire sizing optimization; wire sizing synthesis; CMOS integrated circuits; Clocks; Delay; Impedance; Integrated circuit interconnections; Power dissipation; Power system interconnection; Process design; Signal synthesis; Wire; Characteristic impedance; dynamic power; inductive interconnect; short-circuit power; transient power dissipation; underdamped systems;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2004.834227
  • Filename
    1407949