Title :
A floating well method for exact capacitance-voltage measurement of nano technology
Author :
Su, Hung-Der ; Chiou, Bi-Shiou ; Wu, Shien-Yang ; Chang, Ming-Hsung ; Lee, Kuo-Hua ; Chen, Yung-Shun ; Chao, Chih-Ping ; See, Yee-Chaung ; Sun, Jack Yuan-Chen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
fDate :
6/1/2003 12:00:00 AM
Abstract :
Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.
Keywords :
capacitance measurement; nanotechnology; semiconductor device measurement; capacitance-voltage measurement; electrical oxide thickness; floating well method; inversion capacitance; nanotechnology; parasitic capacitance; ultrathin oxide device; Bonding; Capacitance measurement; Capacitance-voltage characteristics; Chaos; Distortion measurement; Frequency; Leakage current; Parasitic capacitance; Semiconductor device manufacture; Sun;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2003.813329
