Title :
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications
Author :
Wang, Chua-Chin ; Tseng, Yih-Long ; She, Hsien-Chih ; Hu, Ron
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. The design is carried out by TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the voltage-controlled delay tap line at the midway of the working range. Meanwhile, the power dissipation is 52.5 mW at 1.2 GHz output.
Keywords :
CMOS integrated circuits; delay lock loops; frequency measurement; frequency multipliers; programmable circuits; radiocommunication; radiofrequency integrated circuits; voltage-controlled oscillators; 1.2 GHz; 100 to 150 MHz; 2.5 V; 52.5 mW; CMOS local oscillator; TSMC 1P5M CMOS process; delayed lock loop; power dissipation; programmable DLL based frequency multiplier; voltage controlled delay tap line; wireless applications; CMOS process; Clocks; Delay effects; Delay lines; Frequency locked loops; Frequency measurement; Local oscillators; Power dissipation; Power supplies; Voltage; DLL; frequency multiplier; programmable;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2004.837997
