Title :
Optimal design for a ball grid array wire bonding process using a neuro-genetic approach
Author :
Su, Chao-Ton ; Chiang, Tai-Lin
Author_Institution :
Dept. of Ind. Eng. & Manage., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
1/1/2002 12:00:00 AM
Abstract :
This study presents an integrated method in which neural networks, genetic algorithms, and exponential desirability functions are used to optimize the ball grid array (BGA) wire bonding process. As widely anticipated, the BGA package will become the fastest-growing semiconductor package and push integrated circuit (IC) packaging to higher level of compactness and density. However, wire bonding in BGA is difficult owing to its high input/output (I/O) count, fine pitch wire bonds, and long wire lengths. This study addresses two fundamental issues in the semiconductor assembly facility on its quest toward a defect-free manufacturing environment. First, the problem of exploring the nonlinear multivariate relationship between parameters and responses and second, obtaining the optimum operation parameters with respect to each response in which the process should operate. The implementation for the proposed method was carried out in an IC assembly factory in Taiwan; results in this study demonstrate the practicability of the proposed approach
Keywords :
ball grid arrays; electronic engineering computing; fine-pitch technology; genetic algorithms; integrated circuit manufacture; integrated circuit packaging; lead bonding; neural nets; BGA wire bonding process; IC assembly factory; IC packaging; ball grid array; defect-free manufacturing environment; exponential desirability functions; fine pitch wire bonds; genetic algorithms; integrated circuit packaging; integrated method; microassembly; neural networks; nonlinear multivariate relationship; optimal design; optimum operation parameters; semiconductor assembly facility; Assembly; Bonding processes; Electronics packaging; Genetic algorithms; Integrated circuit packaging; Neural networks; Optimization methods; Semiconductor device manufacture; Semiconductor device packaging; Wire;
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
DOI :
10.1109/TEPM.2002.1000478