DocumentCode
745524
Title
Low power clock generator based on area-reduced interleaved synchronous mirror delay
Author
Sung, Kihyuk ; Yang, Byung-Do ; Kim, Lee-Sup
Author_Institution
Dept. of Electron. Eng. & Comput. Sci., KAIST, Daejeon, South Korea
Volume
38
Issue
9
fYear
2002
fDate
4/25/2002 12:00:00 AM
Firstpage
399
Lastpage
400
Abstract
A new interleaved synchronous mirror delay (SMD) is proposed to reduce circuit size. In addition, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD
Keywords
SPICE; VLSI; circuit simulation; clocks; delay circuits; delays; integrated circuit design; logic gates; low-power electronics; synchronisation; HSPICE simulation; VLSI systems; area reduction; area-reduced interleaved synchronous mirror delay; circuit size reduction; clock synchronisation; interleaved SMD; interleaved synchronous mirror delay; inverter; low power clock generator; polarity problem; power reduction; simulation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020293
Filename
1001535
Link To Document