Title :
A dual-port FASTBUS memory to test the L3 data acquisition system
Author :
Cristofori, P.P. ; Cesaroni, F. ; Falciano, S. ; Medici, G.
Author_Institution :
Univ. degli Studi La Sapienza, Roma, Italy
fDate :
4/1/1988 12:00:00 AM
Abstract :
A dual-port 0.25-Mbytes (64 K×32 bits) FASTBUS memory module is described which implements a large set of functions on the Crate Port, while the Cable Port is mainly used for data transfers. Both linear and circular FIFO-like modes are software-selectable. Two pointers are available for write and read operations, respectively. The memory, successfully used to test the L3 event builders, exhibits features of an interesting, general purpose, FASTBUS module for event buffering in large data acquisition systems
Keywords :
buffer storage; computer interfaces; data acquisition; integrated memory circuits; 0.25 MB; 32 bits; Cable Port; Crate Port; FIFO-like modes; L3 data acquisition system; L3 event builders; dual-port FASTBUS memory; event buffering; pointers; read operations; write operations; Buffer storage; Communication cables; Control systems; Costs; Data acquisition; Detectors; Fastbus; Memory architecture; Superluminescent diodes; System testing;
Journal_Title :
Nuclear Science, IEEE Transactions on
