A high-voltage output driver in a 2.5-V 0.25-μm CMOS technology

Author

Serneels, Bert ; Piessens, Tim ; Steyaert, Michiel ; Dehaene, Wim

Author_Institution

ESAT-MICAS Lab., Katholieke Univ. Leuven, Belgium

Volume

40

Issue

3

fYear

2005

fDate

3/1/2005 12:00:00 AM

Firstpage

576

Lastpage

583

Abstract

The design of a high-voltage output driver in a digital 0.25-μm 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-Ω load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 Ω.

Keywords

CMOS digital integrated circuits; buffer circuits; driver circuits; high-voltage techniques; hot carriers; 0.25 micron; 10 MHz; 2.5 V; 250 kHz; 50 ohm; 6.46 V; 7.5 V; 70 kHz; CMOS integrated circuits; PWM signal; buffer circuits; dual-tone sinusoid; high-voltage output driver; high-voltage techniques; hot carrier degradation; nominal supply voltage; oxide stress; self-biased cascode topology; stacked devices; switching output stage; CMOS process; CMOS technology; Circuit topology; Costs; Degradation; Driver circuits; Integrated circuit technology; Pulse width modulation; Transistors; Voltage; Buffer circuits; CMOS integrated circuits; high-voltage techniques;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.843599

Filename

1408077