Development, Design and Characterization of a Novel Protocol and Interfaces for the Control and Readout of Front-End Electronics in High Energy Physics Experiments

The new FF-LYNX communication protocol, aiming at the fulfillment of non-homogeneous latency and bandwidth requirements of future High Energy Physics experiments, as well as its implementation into IP Cores available for ASICs development, are described in this paper. The first test-chip implementing FF-LYNX IP-Cores has been designed in the IBM 130 nm CMOS technology, adopting radiation hardening techniques. Transmitter and Receiver interfaces, designed in three different speed options, 4 × F, 8 × F and 16 × F (F=reference clock frequency), as well as different rad-hard FIFOs, constitute the overall architecture of the testchip. A detailed analysis of the area, power consumption and speed has been performed besides the functional characterization, by means of a configurable test-bed. X-ray irradiation tests have been carried out at CERN facilities to verify the Total Ionization Dose hardness of the interfaces, with their full functionality up to 40 Mrad(SiO₂).