Recursive bitstream conversion: third-order structures

Author

Roza, Engel ; Birru, Dagnachew

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

49

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

591

Lastpage

601

Abstract

Presents a stability analysis of third-order recursive bitstream converters. It also unifies the algorithm-based concept of recursive bitstream conversion with the structure-based concept of reduced sample-rate sigma-delta modulation. These concepts can both be viewed as generalized sigma-delta modulation with the attractive property that the clock rate within the loop is an "integer fraction" of the bitstream rate as a result of the out-of-loop position of the parallel-to-series or series-to-parallel converter. Both the conversion from a low-sample rate, high-precision signal format to the bitstream format and its inverse have been analyzed. The results of the analyses are demonstrated on a design study of a transceiver for ANSI HDSL2. The developed theory can easily be applied to fourth-order and higher-order structures as well

Keywords

circuit stability; digital subscriber lines; recursive estimation; sigma-delta modulation; transceivers; ANSI HDSL2; bitstream rate; clock rate; generalized sigma-delta modulation; out-of-loop position; parallel-to-series converter; recursive bitstream conversion; reduced sample-rate sigma-delta modulation; series-to-parallel converter; signal format; stability analysis; third-order structures; transceiver; Bit rate; Circuits; Clocks; Digital modulation; Frequency conversion; Laboratories; Sampling methods; Signal analysis; Signal to noise ratio; Stability analysis;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/TCSI.2002.1001948

Filename

1001948