Title :
A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links
Author :
Toifl, Thomas ; Menolfi, Christian ; Buchmann, Peter ; Kossel, Marcel ; Morf, Thomas ; Reutemann, Robert ; Ruegg, Michael ; Schmatz, Martin L. ; Weiss, Jonas
Author_Institution :
IBM Zurich Res. Lab., Rueschlikon, Switzerland
Abstract :
A novel architecture for clock generation in dual-loop subrate clock and data recovery (CDR) circuits is proposed based on an adjustable phase-locked loop (PLL). The adjustable PLL (adjPLL) generates eight equidistant clock phases, whose timing with respect to a reference clock can be simultaneously shifted in steps of 3 ps, controllable by a digital value. The programmable phase shift is achieved by adding the weighted outputs of several XOR phase detectors. The measured tracking jitter of the PLL, fabricated in 90-nm SOI CMOS, is 0.94 ps rms at 2.5 GHz, and the power consumption is 20 mW at VDD=0.9 V. The circuit occupies an area of only 0.016 mm2.
Keywords :
CMOS digital integrated circuits; clocks; digital phase locked loops; jitter; programmable circuits; silicon-on-insulator; 0.94 ps; 2.5 GHz; 20 mW; 9 V; 90 nm; SOI CMOS; adjustable phase-locked loop; clock and data recovery circuits; clock generation; clock phase generation; digital programmable phase shift; multiphase generator phase locked loop; serial links; tracking jitter; Area measurement; Circuits; Clocks; Detectors; Digital control; Jitter; Phase detection; Phase locked loops; Power measurement; Timing; Clock and data recovery (CDR); XOR; phase detector; phase interpolator; phase-locked loop (PLL);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.856581
