A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback

Author

Dalton, Declan ; Chai, Kwet ; Evans, Eric ; Ferriss, Mark ; Hitchcox, Dave ; Murray, Paul ; Selvanayagam, Sivanendra ; Shepherd, Paul ; DeVito, Lawrence

Author_Institution

Analog Devices, Limerick, Ireland

Volume

40

Issue

12

fYear

2005

Firstpage

2713

Lastpage

2725

Abstract

A continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described. The circuit automatically detects a change in input data rate, acquires the new frequency, and reports the data rate to the user without the need for an external reference clock or any programming. At 2.5Gb/s, it achieves an acquisition time of 1 ms. In tracking mode, it uses a dual DLL/PLL to provide superior jitter performance compared to a standard second-order loop. At the OC48 data rate, it achieves a jitter transfer bandwidth of 500 kHz and a jitter tolerance bandwidth of 3 MHz. It is on a 0.35-μm double-poly, triple-metal (DPTM) BiCMOS process, dissipates 235 mA from a 3.3-V supply, and occupies 9 mm². It is in a compact 5×5 mm² LFCSP package.

Keywords

BiCMOS digital integrated circuits; clocks; delay lock loops; detector circuits; phase locked loops; 0.35 micron; 12.5 to 2700 Mbits/s; 2.5 Gbit/s; 235 mA; 3 MHz; 3.3 V; 500 kHz; automatic frequency acquisition; clock and data recovery circuit; continuous-rate CDR; data-rate readback; delay-locked loop; double-poly triple-metal BiCMOS process; dual DLL-PLL; phase-locked loop; Automatic frequency control; Automatic programming; Bandwidth; Circuits; Clocks; Frequency locked loops; Jitter; Optical receivers; Phase locked loops; SONET; Clock and data recovery (CDR); delay-locked loop (DLL); frequency-locked loop (FLL); phase-locked loop (PLL);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.856577

Filename

1546246