Title :
A hierarchical infrastructure for SoC test management
Author :
Benso, Alfredo ; Di Carlo, Stefano ; Prinetto, Paolo ; Zorian, Yervant
Author_Institution :
Politecnico di Torino, Italy
Abstract :
HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.
Keywords :
built-in self test; integrated circuit testing; system-on-chip; BIST scheduling; SoC test management; TAM architecture; built-in test architectures; hierarchical infrastructure; systems on chip; test access method; Built-in self-test; Communication system control; Control systems; Design methodology; Design optimization; High definition video; Logic testing; Protocols; Strategic planning; System testing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1214350
