• DocumentCode
    746639
  • Title

    New memoryless, mod (2n+or-1) residue multiplier

  • Author

    Hiasat, A.

  • Volume
    28
  • Issue
    3
  • fYear
    1992
  • Firstpage
    314
  • Lastpage
    315
  • Abstract
    A mod (2n+or-1) residue multiplier is introduced. This multiplier does not use any memory. Using VLSI components, a very high speed multiplier is achieved. The whole implementation consists of a binary multiplier, adder and a few logic gates. This implies a reduced hardware requirement.
  • Keywords
    VLSI; digital arithmetic; multiplying circuits; VLSI components; adder; binary multiplier; hardware requirement; logic gates; residue multiplier;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19920194
  • Filename
    121445
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=746639