Title :
Long-term bias temperature reliability of P+ polysilicon gated FET devices
Author :
Abadeer, Wagdi W. ; Tonti, William R. ; Hänsch, Wilfried E. ; Schwalke, Udo
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
fDate :
2/1/1995 12:00:00 AM
Abstract :
An instability was found to be associated with +BT stress for P + poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N+ poly-gated devices (NNMOS and NPMOS). The instability with the P+ poly-gated devices, which is a decrease in threshold voltage (Vt) and an increase in interface state density (Dit), was significantly reduced following N2 annealing at 400°C. It is shown that adequate reliability for P+ poly-gated devices can be achieved for VLSI technologies
Keywords :
CMOS integrated circuits; MOSFET; VLSI; annealing; elemental semiconductors; integrated circuit reliability; interface states; semiconductor device reliability; silicon; 400 C; N2; N2 annealing; NMOSFETs; P+ polysilicon gated FET devices; PMOSFETs; Si; VLSI technologies; instability; interface state density; long-term bias temperature reliability; threshold voltage; Electric resistance; FETs; Fingers; Heterojunction bipolar transistors; Power amplifiers; Power dissipation; Solids; Temperature; Thermal conductivity; Thermal resistance;
Journal_Title :
Electron Devices, IEEE Transactions on
