A new method for extracting base resistance in bipolar transistors

The base resistance extraction method presented by Linder and coworkers (2001) requires an array of dual-base npn test structures to separate the intrinsic base resistance from its extrinsic counterpart (denoted as R_BI and R_BX, respectively). This requirement imposes real-estate constraints, especially when the nonproduct silicon area is limited. In contrast, we propose a new technique for R_BI and R_BX extraction using only one (rather than multiple) dual-base devices. The physics behind this technique is that current injection swings from one side of the emitter window to the other as a result of a polarity switch of the dc bias difference (ΔV_B) between the two separate bases. Specifically, as a constant current I_E is pulled out of the emitter, the emitter voltage (V_E) is monitored as a function of ΔV_B. A closed-form solution for the partial derivative of V_E with respect to ΔV_B is derived from a physics-based model. The solution predicts that k₁+k₂=1 and R_BI/R_BX=k₁/k₂-1, where k₁ and k₂ are defined as the asymptotic values of the V_E versus ΔV_B slopes at very high positive and negative ΔV_B, respectively. A dual-base test structure with an emitter size of 0.4×4.0 μm² is fabricated using a self-aligned, double-poly process, and k₁=0.85 and k₂=0.15 are extracted. As a result, we obtain R_BI/R_BX=4.67 and an intrinic base sheet resistance of 15.7 kΩ/□.