Title :
An architecture for a nondeterministic distributed simulator
Author :
Bumble, Marc ; Coraor, Lee D.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fDate :
5/1/2002 12:00:00 AM
Abstract :
A computer architecture for an accelerated, parallel, nondeterministic, discrete event simulator is described. The machine is evaluated for accelerating: road traffic simulation. The architecture employs reconfigurable logic, systolic arrays, and a reduction bus to perform microscopic discrete event simulation. The simulator, which achieves a speedup factor of at least 91 over its traffic software counterpart, is fast enough to be practical to municipal traffic management engineers handling road incidents in large metropolitan traffic networks
Keywords :
discrete event simulation; reconfigurable architectures; road traffic; systolic arrays; FPGA; accelerated discrete event simulator; computer architecture; field programmable gate arrays; metropolitan traffic networks; municipal traffic management; nondeterministic distributed simulator architecture; parallel simulator; reconfigurable logic; reduction bus; road incidents; road traffic simulation; simulation machine; speedup factor; systolic arrays; traffic software; Acceleration; Computational modeling; Computer architecture; Computer simulation; Discrete event simulation; Reconfigurable logic; Roads; Systolic arrays; Telecommunication traffic; Traffic control;
Journal_Title :
Vehicular Technology, IEEE Transactions on
DOI :
10.1109/TVT.2002.1002496
