A new polysilicon CMOS self-aligned double-gate TFT technology

Author

Xiong, Zhibin ; Liu, Haitao ; Zhu, Chunxiang ; Sin, Johnny K O

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China

Volume

52

Issue

12

fYear

2005

Firstpage

2629

Lastpage

2633

Abstract

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 Å) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V_gs=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V_gs=-20V) compared to the conventional single-gate device.

Keywords

CMOS integrated circuits; thin film transistors; 20 V; CMOS; backlight exposure technique; current saturation; n-channel device; p-channel device; polysilicon thin film transistor; self-aligned double-gate TFT technology; single-gate TFT; thick source/drain region; ultrathin channel region; Active matrix liquid crystal displays; Active matrix technology; CMOS technology; Chemical technology; Fabrication; Integrated circuit technology; Leakage current; Numerical simulation; Silicon compounds; Thin film transistors; CMOS; double-gate (DG); polysilicon thin-film transistor (TFT); self-aligned (SA);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2005.859686

Filename

1546325