Title :
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
Author :
Huang, Chao-Tsung ; Tseng, Po-Chih ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
4/1/2005 12:00:00 AM
Abstract :
In this paper, a detailed analysis of very large scale integration (VLSI) architectures for the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is presented in many aspects, and three related architectures are proposed as well. The 1-D DWT and inverse DWT (IDWT) architectures are classified into three categories: convolution-based, lifting-based, and B-spline-based. They are discussed in terms of hardware complexity, critical path, and registers. As for the 2-D DWT, the large amount of the frame memory access and the die area occupied by the embedded internal buffer become the most critical issues. The 2-D DWT architectures are categorized and analyzed by different external memory scan methods. The implementation issues of the internal buffer are also discussed, and some real-life experiments are given to show that the area and power for the internal buffer are highly related to memory technology and working frequency, instead of the required memory size only. Besides the analysis, the B-spline-based IDWT architecture and the overlapped stripe-based scan method are also proposed. Last, we propose a flexible and efficient architecture for a one-level 2-D DWT that exploits many advantages of the presented analysis.
Keywords :
VLSI; computational complexity; convolution; discrete wavelet transforms; signal classification; splines (mathematics); 1D discrete wavelet transform; 2D discrete wavelet transform; B-spline factorization; VLSI architecture; computational complexity; lifting scheme; signal convolution; very large scale integration; Bandwidth; Chaos; Convolution; Discrete wavelet transforms; Educational institutions; Hardware; Memory architecture; Registers; Very large scale integration; Wavelet analysis; B-spline factorization; VLSI architecture; discrete wavelet transform; lifting scheme; line-based method;
Journal_Title :
Signal Processing, IEEE Transactions on
DOI :
10.1109/TSP.2005.843704