DocumentCode :
747443
Title :
Heterogeneous Behavioral Hierarchy Extensions for SystemC
Author :
Patel, Hiren D. ; Shukla, Sandeep K. ; Bergamaschi, Reinaldo A.
Author_Institution :
Electr. & Comput. Eng. Dept., Virginia Polytech. Inst. & State Univ., Blacksburg, VA
Volume :
26
Issue :
4
fYear :
2007
fDate :
4/1/2007 12:00:00 AM
Firstpage :
765
Lastpage :
780
Abstract :
System level design methodology and language support for high-level modeling enhances productivity for designing complex embedded systems. For an effective methodology, efficiency of simulation and a sound refinement-based implementation path are also necessary. Although some of the recent system level design languages (SLDLs) such as SystemC, SystemVerilog, or SpecC have features for system level abstractions, several essential ingredients are missing from these. We consider: 1) explicit support for multiple models of computation (MoCs) or heterogeneity so that distributed reactive embedded systems with hardware and software components can be easily modeled; 2) the ability to build complex behaviors by hierarchically composing simpler behaviors and the ability to distinguish between structural and heterogeneous behavioral hierarchy; and 3) hierarchical composition of behaviors that belong to distinct MoCs, as essential for successful SLDLs. One important requirement for such an SLDL should be that the simulation semantics are compositional, and hence no flattening of hierarchically composed behaviors are needed for simulation. In this paper, we show how we designed SystemC extensions to facilitates for heterogeneous behavioral hierarchy, compositional simulation semantics, and a simulation kernel that shows up to 40% more efficient than standard SystemC simulation
Keywords :
circuit simulation; embedded systems; high level synthesis; logic design; specification languages; SystemC; behavioral decomposition; compositional simulation semantics; distributed reactive embedded systems; heterogeneous behavioral hierarchy; hierarchical finite state machine; hierarchical synchronous data flow; high-level modeling; language support; multiple models of computation; simulation kernel; structural modeling; system level abstractions; system level design; Circuit simulation; Computational modeling; Design methodology; Embedded computing; Embedded software; Embedded system; Hardware design languages; Productivity; Software systems; System-level design; Behavioral decomposition; SystemC; behavioral modeling; embedded system design; heterogeneous behavioral hierarchy; hierarchical finite state machine (HFSM); hierarchical synchronous data flow (SDF); models of computation (MoCs); simulation efficiency; structural modeling; system level designs;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2006.884859
Filename :
4135373
Link To Document :
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