Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits

Author

Paul, Bipul C. ; Kang, Kunhyuk ; Kufluoglu, Haldun ; Alam, Muhammad A. ; Roy, Kaushik

Author_Institution

Toshiba America Res. Inc, San Jose, CA

Volume

26

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

743

Lastpage

751

Abstract

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years

Keywords

integrated circuit reliability; integrated logic circuits; nanoelectronics; thermal stability; design for reliability; logic circuits; nanoscale circuit reliability; negative bias temperature instability; sizing algorithm; temporal delay degradation; temporal reliability degradation; threshold-voltage degradation; CMOS technology; Degradation; Delay estimation; Digital circuits; Logic circuits; MOSFETs; Negative bias temperature instability; Niobium compounds; Threshold voltage; Titanium compounds; Design for reliability; negative bias temperature instability (NBTI); performance degradation; threshold-voltage degradation;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2006.884870

Filename

4135374