Design of a-Si TFT demultiplexers for driving gate lines in active matrix arrays

Two a-Si thin-film transistors (TFTs) demultiplexer circuits, resistive load (RL) and complementary-like logic (CLL), are proposed and compared with the conventional pass transistor logic (PTL) demultiplexer circuit. Analytical and experimental results indicate that the proposed RL and CLL demultiplexers outperform the PTL circuit by providing larger output voltage swings (OVSs), faster dynamic responses, and less OVS sensitivities to the device instability. The pulse-bias stress experiments, simulating the normal condition of operation, are conducted both on individual a-Si TFTs and a-Si TFT demultiplexer circuits, and the variations in device/circuit electrical characteristics are measured during 12 h. The measurement results indicate that the OVS degradation of proposed circuits can be limited to 7 mV/h, suggesting a long circuit lifetime.