Title :
A knowledge-based test generator for standard cell and iterative array logic circuits
Author :
Varma, Prab ; Tohma, Yoshihiro
Author_Institution :
GEC Res. Ltd., Wembley, UK
fDate :
4/1/1988 12:00:00 AM
Abstract :
The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high-level test knowledge in conjunction with low-level structural information to generate tests for the circuit.
Keywords :
PROLOG; VLSI; automatic test equipment; cellular arrays; expert systems; integrated circuit testing; integrated logic circuits; ASIC; IC testing; Prolog; Protean; automatic test generator; cell test generator; custom IC; generates test knowledge; hierarchical test generator; high-level test knowledge; iterative array logic circuits; iterative logic arrays; knowledge-based test generator; low-level structural information; propagation characteristics; scan-designed standard cell VLSI circuits; standard cell array logic; stuck-at faults; Automatic logic units; Automatic test pattern generation; Automatic testing; Character generation; Circuit faults; Circuit testing; Logic arrays; Logic circuits; Logic testing; Test pattern generators; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
