• DocumentCode
    748245
  • Title

    Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint

  • Author

    Wang, Sying-Jyan ; Li, Katherine Shu-Min ; Chen, Shih-Cheng ; Shiu, Huai-Yan ; Chu, Yun-Lung

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Nat. Chung Hsing Univ., Taichung
  • Volume
    28
  • Issue
    5
  • fYear
    2009
  • fDate
    5/1/2009 12:00:00 AM
  • Firstpage
    716
  • Lastpage
    727
  • Abstract
    The degree of achievable test-data compression depends on not only the compression scheme but also the structure of the applied test data. Therefore, it is possible to improve the compression rate of a given test set by carefully organizing the way that test data are present in the scan structure. The relationship between signal probability and test-data entropy is explored in this paper, and the results show that the theoretical maximum compression can be increased through a partition of scan flip-flops such that the test data present in each partition have a skewed signal distribution. In essence, this approach simply puts similar scan flip-flops in an adjacent part of a scan chain, which also helps to reduce shift power in the scan test process. Furthermore, it is shown that the intrapartition scan-chain order has little impact on the compressibility of a test set; thus, it is easy to achieve higher test compression with low routing overhead. Experimental results show that the proposed partition method can raise the compression rates of various compression schemes by more than 17%, and the average reduction in shift power is about 50%. In contrast, the increase in routing length is limited.
  • Keywords
    VLSI; flip-flops; integrated circuit testing; high test-data compressibility; routing constraint; scan flip-flops; scan-chain partition; test-data entropy; very large scale integration circuits; Entropy theory; routing; scan-based design; test power; test-data compression;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2009.2015741
  • Filename
    4838825