Compact modeling of thermal resistance in bipolar transistors on bulk and SOI substrates

Author

Pacelli, Andrea ; Palestri, Pierpaolo ; Mastrapasqua, Marco

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA

Volume

49

Issue

6

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

1027

Lastpage

1033

Abstract

Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design

Keywords

bipolar transistors; circuit CAD; heating; isolation technology; semiconductor device models; silicon-on-insulator; thermal analysis; thermal resistance; 3D device simulation; SOI substrates; Si-SiO₂; bipolar transistors; bulk substrates; computer-aided design; deep-trench isolation; modeling; multiple emitter fingers; shallow-trench isolation; thermal resistance; Bipolar transistors; Computational modeling; Dielectric substrates; Equations; MOSFETs; Silicon on insulator technology; Solid modeling; Thermal conductivity; Thermal resistance; Two dimensional displays;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2002.1003724

Filename

1003724