Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25°C to 125°C) of the four components of off-state drain leakage (I_off ) (i.e. subthreshold leakage (I_sub), gate edge-direct-tunneling leakage (I_EDT), gate-induced drain-leakage (I_GIDL), and bulk band-to-band-tunneling leakage (I_B-BTBT)). In addition, the high temperature characteristics of I_off with reverse body bias (V_B) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 μm, 0.15 μm, and 0.13 μm). Experiments show that the optimum V_B, which minimizes I_off, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I_B-BTBT and I_GIDL by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I_G-on) and I_EDT specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I_SB) is also analyzed