Optimal usage of CMOS within a BiCMOS technology

The comparison of CMOS to BiCMOS often seen in the literature shows the delays of single-stage circuits driving a capacitive load, with the BiCMOS circuit exhibiting a bold advantage. This comparison is misleading, and it suggests that the highest possible performance chip design implemented in a BiCMOS technology, should use only BiCMOS circuits. When multistage circuits and chip wiring resistance are also considered, CMOS performance is found to be much closer to BiCMOS performance. CMOS circuits are shown to be preferred over BiCMOS circuits for a significant fraction of the chip nets. When nets that can afford a performance decrease are relaxed by using CMOS circuits instead of BiCMOS circuits, the CMOS fraction increases further. High usage of CMOS is desirable for area and yield considerations. Evaluations of the optimal CMOS role in future-generation BiCMOS technologies are expected to show an even larger role for CMOS