Title :
Background digital calibration of successive approximation adc with adaptive equalisation
Author :
Liu, W. ; Chiu, Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL
Abstract :
An equalisation-based digital background error-correction technique for successive approximation analogue-to-digital converters (SA-ADCs) is presented. This technique enables the size of the sampling capacitors to be scaled down to the kT/C limit without matching concerns. Therefore, for SA-ADCs with resolutions of 10 bits and above, the proposed low-cost, power-efficient digital calibration technique indicates a large power saving and scalability improvement in deeply scaled CMOS technology. Computer simulation validates the effectiveness of this technique for a SA-ADC with 12-bit resolution and 10% mismatch in its digital-to-analogue converter component. The effective number of bits is improved from 4.8 to 12.
Keywords :
CMOS digital integrated circuits; adaptive equalisers; analogue-digital conversion; calibration; capacitors; error correction; 12-bit resolution; adaptive equalisation; background digital calibration; computer simulation; deeply scaled CMOS technology; digital background error-correction technique; digital-to-analogue converter; power saving; sampling capacitors; scalability improvement; successive approximation analogue-to-digital converters;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2009.2374