DocumentCode
751351
Title
Architecture and Construction of a Hardware Sequential Encoder for Speech
Author
Anderson, J.B. ; Ho, C-W P.
Author_Institution
Dept. of Elec. Engr. and the Comm. Res. Lab.,McMaster University,Ont.,Canada
Volume
25
Issue
7
fYear
1977
fDate
7/1/1977 12:00:00 AM
Firstpage
703
Lastpage
707
Abstract
Recent work has shown the usefulness of sequential or "tree" encoding of speech. We report on construction of a TTL hardware multi-path sequential encoder which uses the so-called 
algorithm search procedure. The device attains a signal-to-noise ratio of about 20 dB at 16 kbits/s. Hardware peculiar to this type of encoder is discussed, including architecture of the search algorithm sorter, the squared error calculator, and the code generator.
algorithm search procedure. The device attains a signal-to-noise ratio of about 20 dB at 16 kbits/s. Hardware peculiar to this type of encoder is discussed, including architecture of the search algorithm sorter, the squared error calculator, and the code generator.Keywords
Bipolar integrated circuits, logic; Sequential coding; Speech coding; Algorithm design and analysis; Communications Society; Data communication; Delay; Encoding; Hardware; Phase change materials; Signal to noise ratio; Speech; Tree graphs;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/TCOM.1977.1093894
Filename
1093894
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