Continuous time sigma-delta modulator based on binary weighted charge balance

A novel multibit continuous time sigma-delta modulator architecture that does not require a flash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.