Title :
Model for propagation delay evaluation of CMOS inverter including input slope effects for timing verification
Author :
Chow, H.C. ; Feng, Wu-Shiung
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
fDate :
6/4/1992 12:00:00 AM
Abstract :
A propagation delay model of a short-channel CMOS inverter is reported, which considers input slope effects for timing verification by semi-empirical coefficients. Model calculations which demonstrate the source-drain series resistance effect show good agreement with SPICE MOS level 3 simulations.
Keywords :
CMOS integrated circuits; digital simulation; integrated logic circuits; invertors; logic CAD; SPICE MOS level 3 simulations; input slope effects; propagation delay evaluation; semi-empirical coefficients; short-channel CMOS inverter; source-drain series resistance effect; timing verification;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920731
