A readout unit for high rate applications

The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via the PCI bus, which is hosted by a networked microprocessor card. Its main tasks are remote FPGA configuration and initialization of the PCI cards. The RU hardware architecture has been optimized for a throughput of up to 200 MB/s at a 1 MHz trigger rate, as required by the most demanding application, the LHCb level-1 trigger network. A custom traffic-scheduling link is available for applications like pipelined destination address allocation