3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

Author

Yano, Kazuo ; Hiraki, Mitsuru ; Shukuri, Shohji ; Hanawa, Makoto ; Suzuki, Makoto ; Morita, Satoru ; Kawamata, Atsushi ; Ohki, Nagatoshi ; Nishida, Takashi ; Seki, Koichi

Author_Institution

Center for Solid-State Electron. Res., Arizona State Univ., Tempe, AZ, USA

Volume

27

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

373

Lastpage

381

Abstract

A quasi-complementary BiCMOS gate for low-voltage supply is applied to a 3.3V RISC data path. For a parallel RISC processor, the major issues are the construction of arithmetic modules in a small number of transistors and the shortening of the cycle time as well as the delay time. The feedbacked massive-input logic (FML) concept is proposed to meet these requirements. It reduces the number of transistors and the power within the framework of fully static logic 3-4 times. A low-voltage BiCMOS D-flip-flop is also conceived to allow the single-phase clocking scheme, which is favorable for high-frequency operation of RISCs. To demonstrate these circuit techniques, a 32-b ALU is designed and fabricated using 0.3-μm BiCMOS to demonstrate 1.6 times performance leverage over CMOS at 3.3 V

Keywords

BIMOS integrated circuits; digital arithmetic; flip-flops; logic circuits; logic design; reduced instruction set computing; 0.3 micron; 250 MHz; 3.3 V; 32 bit; ALU; D-flip-flop; RISC; arithmetic logic unit; arithmetic modules; circuit techniques; feedbacked massive-input logic; fully static logic; high-frequency operation; low-voltage supply; quasi-complementary BiCMOS gate; single-phase clocking scheme; Arithmetic; BiCMOS integrated circuits; CMOS technology; Delay effects; Laboratories; Logic; Microprocessors; Modular construction; Reduced instruction set computing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.121560

Filename

121560