A submicrometer CMOS embedded SRAM compiler

Author

Tou, Jarvis C. ; Gee, Perry ; Duh, John ; Eesley, Richard

Author_Institution

Motorola Inc., Chandler, AZ, USA

Volume

27

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

417

Lastpage

424

Abstract

A highly flexible memory generation system that produces high-density synchronous single- or dual-port static memories has been developed using a 0.7-μm L_eff CMOS technology. The fully diffused memories are embedded into a gate-array environment. Configurations upwards of 1K words×256 b and 16K words×16 b have been obtained. Single-port address access times are, for example, 6.2 ns for 8K and 6.9 ns for 32K SRAMs. The Memorist SRAM Compiler provides for accurate timing characterization and is tightly integrated into an ASIC design CAD system. A gate-array-based test-chip cluster consisting of four 7.3×7.3 mm dies with 16 embedded diffused memories has also been developed

Keywords

CMOS integrated circuits; SRAM chips; VLSI; circuit layout CAD; logic arrays; 0.7 micron; 6.9 ns; 8 to 256 kbit; ASIC design CAD system; CMOS; Memorist SRAM Compiler; address access times; dual-port static memories; embedded SRAM compiler; fully diffused memories; gate-array environment; gate-array-based test-chip; memory generation system; submicrometer CMOS; timing characterization; Application specific integrated circuits; CMOS technology; Density measurement; Design automation; Packaging; Random access memory; Synchronous generators; Testing; Timing; Velocity measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.121565

Filename

121565