A study of deep-submicron MOSFET scaling based on experiment and simulation

The scaling relationships among three fundamental quantities of deep-submicron MOSFET´s, i.e., effective channel length L_eff, device speed g_m/WC_ox, and drain-induced barrier lowering (DIBL) δV_t/δV_ds, are investigated using both device measurements and numerical simulations. It is found that these relationships can be expressed in power-law forms with excellent statistical significance for both experimental and simulation data samples. The dependence of these scaling relationships on two sets of device parameters is also investigated experimentally and confirmed by numerical simulations. These two sets of parameters are: 1) channel parameters-gate oxide thickness t_ox threshold voltage V_t, and channel doping profile; and 2) source/drain parameters-junction depth x_j, parasitic resistance R_sd , and junction abruptness (e.g., “halo” doping structure). In the deep-submicron regime with L_eff from 0.5 μm down to sub-0.1 μm, it is found that certain relationships among the three fundamental quantities are insensitive or “universal” with respect to particular subsets of device parameters. The relationship between g_m/WC_ox and δV_t/δV_ds with L_eff as an implicit variable is found to be insensitive to t_ox, V_t , and channel doping profile within their respective experimental ranges. The trade-off between device performance (represented by g_m /WC_ox) and short channel effect (represented by δV_t/δV_ds) is dominated by source/drain parameters x_j, R_sd and junction abruptness, rather than channel parameters t_ox, V_t and channel doping profile. Also, the power coefficient relating δV_t/δV_ds, to L_eff is found to be insensitive to t_ox, V_t, and channel doping