Semiconductor Capacitance Penalty per Gate in Single- and Double-Gate FETs

We show that the double-gate (DG) FET geometry has lower gate capacitance per gate C_G and lower sheet carrier density per gate N_S than the single-gate (SG) FET geometry for the same gate-stack because the semiconductor capacitance C_SC is a property of the channel, and therefore, C_SC per gate of the DG FET is one-half that of the SG FET. This effect is marginal in FETs with high effective mass and/or high valley degeneracy channel materials but is fairly pronounced in FETs with low effective mass and/or low valley degeneracy channel materials.