DocumentCode
752247
Title
Design of multigigabit multiplexer-loop-based decision feedback equalizers
Author
Parhi, Keshab K.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Volume
13
Issue
4
fYear
2005
fDate
4/1/2005 12:00:00 AM
Firstpage
489
Lastpage
493
Abstract
This paper presents novel approaches for pipelining of parallel nested multiplexer loops and decision feedback equalizers (DFEs) based on look-ahead techniques. Look-ahead techniques can be applied to pipeline a nested multiplexer loop in many possible ways. It is shown that not all the look-ahead approaches necessarily result in improved performance. A novel look-ahead approach is identified, which can guarantee improvement in performance either in the form of pipelining or parallelism. The proposed technique is demonstrated and applied to design multiplexer-loop-based DFEs with throughput in the range of 3.125-10 Gb/s.
Keywords
decision feedback equalisers; logic design; parallel architectures; pipeline arithmetic; 3.125 to 10 Gbit/s; decision feedback equalizers; look-ahead techniques; parallel nested multiplexer loops; CMOS technology; Decision feedback equalizers; Delay; Equations; Feedback loop; Multiplexing; Parallel processing; Pipeline processing; Throughput; Upper bound; Decision feedback equalizers (DFEs); look-ahead; multiplexer loop; pipelining;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2004.842935
Filename
1411845
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