DocumentCode :
752260
Title :
Memory sub-banking scheme for high throughput MAP-based SISO decoders
Author :
Tiwari, Mayank ; Zhu, Yuming ; Chakrabarti, Chaitali
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Volume :
13
Issue :
4
fYear :
2005
fDate :
4/1/2005 12:00:00 AM
Firstpage :
494
Lastpage :
498
Abstract :
The sliding window (SW) approach has been proposed as an effective means of reducing the memory requirements as well as the decoding latency of the maximum a posteriori (MAP) based soft-input soft-output (SISO) decoder in a Turbo decoder. In this paper, we present sub-banked memory implementations (both single port and dual port) of the SW SISO decoder that achieves high throughput, low decoding latency, and reduced memory energy consumption. Our contributions include derivation of the optimal memory sub-banked structure for different SW configurations, study of the relationship between memory size and energy consumption for different SW configurations and study of the effect of number of sub-banks on the throughput/decoding latency for a given SW configuration.
Keywords :
maximum likelihood decoding; memory architecture; turbo codes; SISO decoders; decoding latency; high throughput MAP; maximum a posteriori; memory energy consumption; memory requirements; memory size; memory sub-banking; sliding window; soft-input soft-output decoder; throughput/decoding latency; turbo decoder; Code standards; Concatenated codes; Delay; Energy consumption; Iterative decoding; Multiaccess communication; Random access memory; Throughput; Turbo codes; Wideband; High throughput; Turbo decoder; memory sub-banking; sliding window (SW); tradeoffs;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2004.842937
Filename :
1411846
Link To Document :
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