• DocumentCode
    752900
  • Title

    Realizing a Sub-Linear Time String-Matching Algorithm With a Hardware Accelerator Using Bloom Filters

  • Author

    Lin, Po-Ching ; Lin, Yin-Dar ; Lai, Yuan-Cheng ; Zheng, Yi-Jun ; Lee, Tsern-Huei

  • Author_Institution
    Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    17
  • Issue
    8
  • fYear
    2009
  • Firstpage
    1008
  • Lastpage
    1020
  • Abstract
    Many network security applications rely on string matching to detect intrusions, viruses, spam, and so on. Since software implementation may not keep pace with the high-speed demand, turning to hardware-based solutions becomes promising. This work presents an innovative architecture to realize string matching in sub-linear time based on algorithmic heuristics, which come from parallel queries to a set of space-efficient Bloom filters. The algorithm allows skipping characters not in a match in the text, and in turn simultaneously inspect multiple characters in effect. The techniques to reduce the impact of certain bad situations on performance are also proposed: the bad-block heuristic, a linear worst-case time method and a non-blocking interface to hand over the verification job to a verification module. This architecture is simulated with both behavior simulation in C and timing simulation in HDL for antivirus applications. The simulation shows that the throughput of scanning Windows executable files for more than 10000 virus signatures can achieve 5.64 Gb/s, while the worst-case performance is 1.2 Gb/s if the signatures are properly specified.
  • Keywords
    C language; digital signatures; field programmable gate arrays; hardware description languages; integrated circuit design; logic design; program verification; string matching; Bloom filter; C language; HDL; algorithmic heuristics; antivirus application; bad-block heuristic; behavior simulation; field programmable gate array; hardware accelerator; linear worst-case time method; network security; nonblocking interface; parallel query; sublinear time string-matching algorithm; timing simulation; verification module; virus signature; Algorithms; field-programmable gate arrays (FPGAs); string matching;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2008.2012011
  • Filename
    4840440