SEU characterization of a hardened CMOS 64K and 256K SRAM

The first single-event-upset (SEU) tests of the AT&T 64K and 256K SRAMs (static random-access memories) have been performed. Feedback resistor values for these parts ranged from 200 kΩ to 1 MΩ. All were fabricated using the 1-μm, 2-level-poly, 2-level-metal process. Ions used for the tests were Ar, Cu, Kr, and Xe, providing a range of effective LET (linear energy transfer) values from 20 to 129 MeV-cm²/mg. With the 64K SRAM operating at 4.5 V and 90°C, an upset threshold LET of 30 MeV-cm²/mg and saturation cross section of 1.5×10^-2 cm² were measured with a nominal room-temperature feedback resistance of 450 kΩ. In Adam´s 10% worst-case environment using the Petersen approximation (see E.L. Petersen et al., ibid., vol.NS-30, p.4533-9, Dec. 1983) this implies an error rate of 1.3×10^-7 errors per bit-day. With a nominal 650-kΩ feedback resistance, a 256K SRAM had a calculated error rate of about 3×10^-8 errors power bit-day at 4.5 V and 90°C. These data agree well with earlier data for a 1 kb test chip. The minimal feedback resistance required to prevent upset versus LET is calculated, using an activation energy of 0.10 eV to estimate the decrease in feedback resistor value as a function of temperature