SEU characterization of hardened CMOS SRAMs using statistical analysis of feedback delay in memory cells

Write-time measurements confirm that the amount of feedback delay introduced by the polysilicon cell resistors in a SEU (single-even-upset) hardened CMOS SRAM (static random-access memory) is not identical for all cells in a memory chip. It is noted that the effect of the variance in the normal distribution of feedback delay has become pronounced because of the large number of resistors in state-of-the-art memory chips. Consequently, statistical analysis of the distribution of feedback delay is useful for proper interpretation of SEU test data to quantify device response for confident hardness assurance. Statistical analysis of the feedback delay distribution in cell arrays using write-time analysis shows that a feedback delay of 6 ns at the temperature of interest is sufficient to harden the AT&T SRAM cell against all LETs (linear energy transfers). To assure the hardness in all cells, however, the mean value must be set higher than the minimum required resistor value. Statistical information about the feedback delay population can be used to calculate the acceptable resistance limits. Alternately, a novel part acceptance plan based on direct electrical measurement of the feedback delay distribution is proposed