• DocumentCode
    753891
  • Title

    Efficient recursive multiply architecture for FPGAs

  • Author

    Perri, S. ; Corsonello, P. ; Cocorullo, G.

  • Author_Institution
    Dept. of Electron., Univ. of Calabria, Rende, Italy
  • Volume
    41
  • Issue
    24
  • fYear
    2005
  • Firstpage
    1314
  • Lastpage
    1316
  • Abstract
    A new methodology for realising efficient multiply architectures for FPGAs is presented. The proposed strategy can be recursively applied to realise larger multipliers. Compared to proprietary macroblocks usually furnished within FPGA development tools, the new approach is more than 45% cheaper and more than 25% faster.
  • Keywords
    circuit CAD; field programmable gate arrays; logic design; multiplying circuits; FPGA; field programmable gate array; recursive multiply architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20053313
  • Filename
    1550107
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=753891