A quasi-analytical SET model for few electron circuit simulation

Author

Mahapatra, Santanu ; Ionescu, Adrian Mihai ; Banerjee, Kaustav

Author_Institution

Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland

Volume

23

Issue

6

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

366

Lastpage

368

Abstract

A novel quasi-analytical model for single electron transistors (SETS) is proposed and validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and transconductance. The new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in both static and dynamic regimes and is attractive for hybrid (SET-CMOS) circuit co-simulation.

Keywords

Monte Carlo methods; circuit simulation; leakage currents; logic simulation; semiconductor device models; single electron transistors; Monte-Carlo simulations; drain current; dynamic regimes; few electron circuit simulation; hybrid circuit cosimulation; logic circuit simulation; parameter extraction; quasi-analytical model; single electron transistors; static regimes; temperature dependent leakage current; Algorithms; Analytical models; Capacitance; Circuit simulation; Logic circuits; Parameter extraction; Single electron transistors; Temperature distribution; Tunneling; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2002.1004237

Filename

1004237