• DocumentCode
    754505
  • Title

    Statistical threshold formulation for dynamic Idd test

  • Author

    Jiang, Wanli ; Vinnakota, Bapiraju

  • Author_Institution
    Test Eng., Guidant Corp., St. Paul, MN, USA
  • Volume
    21
  • Issue
    6
  • fYear
    2002
  • fDate
    6/1/2002 12:00:00 AM
  • Firstpage
    694
  • Lastpage
    705
  • Abstract
    Dynamic Idd techniques can potentially address the limitations of traditional test techniques and the Idd, test. Normal process variations in manufacturing affect dynamic Idd techniques in two ways. Since a fault-free circuit can produce a range of responses, they necessitate the use of a threshold-based test process. Process variations also degrade the resolution and consequently the fault coverage of a test technique. The authors develop statistical techniques to set thresholds in a dynamic Idd test process. The techniques use Principal Component Analysis, a statistical analysis technique,. to identify process corners and compute statistical models. Our techniques are applied to average current-based dynamic tests and to tests based on the energy consumption ratio (ECR). The ECR is a new test metric which offers several advantages, including tolerance to process variations, over other dynamic test techniques. The authors demonstrate that their techniques lead to computationally efficient methods to set accurate thresholds without either significant yield or fault coverage loss. To the best of their knowledge, this is the first systematic technique to set thresholds for a dynamic Idd test method
  • Keywords
    CMOS digital integrated circuits; automatic testing; dynamic testing; fault diagnosis; logic testing; principal component analysis; CMOS; current-based dynamic tests; dynamic Idd test; dynamic test techniques; energy consumption ratio; fault coverage; fault coverage loss; fault-free circuit; logic test techniques; principal component analysis; process corners; process variations; statistical techniques; statistical threshold formulation; test metric; threshold-based test process; Circuit faults; Circuit testing; Degradation; Electrical fault detection; Energy consumption; Integrated circuit testing; Logic testing; Principal component analysis; Statistical analysis; System testing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2002.1004313
  • Filename
    1004313