A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter

Author

Chuang, Shang-Yuan ; Sculley, Terry L.

Author_Institution

Data Acquisition Div., Texas Instruments Inc., Tucson, AZ, USA

Volume

37

Issue

6

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

674

Lastpage

683

Abstract

A digitally self-calibrating pipelined analog-to-digital converter (ADC) featuring 1.5-bit/stage structure is presented. The integral (INL) and differential nonlinearity (DNL) errors are removed using a novel digital calibration algorithm, which also eliminates missing codes that can occur with other calibration algorithms near the extremes of the input range. After calibration, the measured DNL is ±0.6 LSB and the INL is ±2.5 LSB at the 14-bit level. Sampling at a 10-MHz rate, the chip dissipates 220 mW and (post-calibration) yields a signal-to-noise ratio of 77 dB and a spurious-free dynamic range of 95 dB with 4.8-MHz sine wave input signal. The chip is fabricated in 0.5-μm CMOS double-poly double-metal process, measures 3.8 mm × 3.3 mm (150 mil × 130 mil), and operates from a single 5-V supply

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; error correction; pipeline processing; timing jitter; 14 bit; 5 V; CMOS pipelined ADC; charge transferring phase; differential nonlinearity errors; digital calibration algorithm; digitally self-calibrating ADC; double-poly double-metal process; high-speed ADC; integral nonlinearity errors; minimal area overhead; monolithic integrated implementation; operational amplifier design; sample-hold stage; sampling; signal-to-noise ratio; spurious-free dynamic range; timing; Algorithm design and analysis; Analog-digital conversion; CMOS technology; Calibration; Instruments; Operational amplifiers; Pipelines; Power dissipation; Semiconductor device measurement; Ultrasonic imaging;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.1004571

Filename

1004571