Title :
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification
Author :
Zheng, Hao ; Ahrens, Jared ; Xia, Tian
Author_Institution :
Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL
fDate :
7/1/2008 12:00:00 AM
Abstract :
This paper presents a compositional method with failure-preserving abstraction for scalable asynchronous design verification. It combines efficient state-space reductions and novel interface refinement and can dramatically reduce the complexity of state space while decreasing the introduction of false failures. This allows much larger designs to be verified as demonstrated in the experimental results.
Keywords :
asynchronous circuits; logic design; asynchronous design verification; compositional method; failure-preserving abstraction; interface refinement; logic design; model checking; state-space reduction; Computer science; Design methodology; Engineering profession; Explosions; Formal verification; Machine learning; Minimization methods; Productivity; State-space methods; System testing; Abstraction; asynchronous; compositional; formal verification; model checking; refine;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2008.923104
