Efficient tests for realistic faults in dual-port SRAMs

This paper begins with an overview of realistic fault models for dual-port memories, divided into single-port faults and faults unique for dual-port memories. The latter faults cannot be detected with conventional single-port memory tests; they require special tests. A precise notation for all faults, such that ambiguities and misunderstandings are prevented, has been emphasized. Next, the paper presents a methodology to design tests for realistic unique dual-port memory faults, resulting in a set of three linear single-addressing tests which are merged into a single march test (March s2PF), and one linear double-addressing test (March d2PF). March s2PF and March d2PF have been implemented at Intel. The results show that they detect unique faults, i.e., faults that cannot be detected with conventional single-port memory tests. This make them very attractive industrially