Title :
±1.5V 3mW CMOS V--I converter with 75 dB SFDR for 6V/sub pp/ input swings
Author :
López-Martín, A.J. ; Ramirez-Angulo, J. ; Carvajal, R.G.
Author_Institution :
Dept. of Electr. & Electron. Eng., Public Univ. of Navarra
Abstract :
A novel CMOS voltage-to-current converter topology is proposed. The use of nested local feedback loops and the absence of current replication in the signal path provide low sensitivity to transistor mismatch and high linearity. Measurements for a 0.5 mum CMOS prototype show a spurious-free dynamic range (SFDR) of 75 dB for a differential input of 6 Vpp and a dual supply of plusmn1.5 V. The circuit occupies 0.1 mm2 and consumes 3 mW
Keywords :
CMOS integrated circuits; convertors; -1.5 to 1.5 V; 0.5 micron; 3 mW; 6 V; CMOS V-I converter; CMOS voltage-to-current converter topology; high linearity; nested local feedback loops; spurious-free dynamic range; transistor mismatch;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20073939
